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These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54AL
Description: Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset and Clear Features: Inputs Are TTL-Voltage Compatible Outputs Directly Interface to CMOS, NMOS, and TTL Outputs Source/Sink 24 mA Outputs Can Be Tied Directly to VCC or GND for Use in Bus-Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects Schmitt Trigger Action on All Inputs Preset and Clear Inputs Override All Other Inputs High-Impedance Inputs Balanced Propagation Delay and Transition Times Military Temperature Range Available (-55°C to 125°C) Applications: High-Speed Data Storage High-Speed Data Transfer High-Speed Counters High-Speed Shift Registers High-Speed Buffer Registers High-Speed Data Selectors/Multiplexers (For reference only)