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Specifications
SKU: 926107
CAP CERM 15000PF 50V X7R 10%0805
Below is the parameter table and instructions for the AD7248JN, a 12-bit, 2-channel, serial input/output digital-to-analog converter (DAC) from Analog Devices.
AD7248JN Parameter Table
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions |
|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 | 5.5 | V | ||
| Output Range | VOUT | 0 | VDD | V | ||
| Resolution | 12 | bits | ||||
| Differential Nonlinearity | DNL | -1 | 0 | +1 | LSB | |
| Integral Nonlinearity | INL | -1 | 0 | +1 | LSB | |
| Settling Time | tSETTLE | 10 | μs | 0.01% settling | ||
| Power Consumption | IDD | 2.5 | mA | VDD = 5V | ||
| Operating Temperature | Toperating | -40 | +85 | °C | ||
| Storage Temperature | Tstorage | -65 | +150 | °C |
AD7248JN Instructions
Pin Configuration
| Pin | Description |
|---|---|
| VDD | Positive supply voltage |
| VSS | Ground |
| SDI | Serial Data Input |
| SCLK | Serial Clock Input |
| CS | Chip Select (active low) |
| LDAC | Load DAC (active low) |
| VOUT1 | Output Voltage Channel 1 |
| VOUT2 | Output Voltage Channel 2 |
Serial Interface
- Chip Select (CS):
- Active low. When CS is low, the device is selected and ready to receive data.
- Serial Clock (SCLK):
- The clock signal used to shift data into the device. Data is sampled on the rising edge of SCLK.
- Serial Data Input (SDI):
- The input pin for the serial data stream. Data is shifted into the device on the rising edge of SCLK.
- Load DAC (LDAC):
- Active low. When LDAC is low, the data in the internal register is transferred to the DAC registers, updating the output voltages.
Data Format
- The AD7248JN uses a 16-bit serial data format.
- The first 4 bits (D15-D12) are the control bits.
- The next 12 bits (D11-D0) are the data bits for the DAC.
Control Bits (D15-D12)
- D15: Write All Channels (WAC)
- 0: Write to both channels.
- 1: Write to a single channel.
- D14: Channel Select (CHSEL)
- 0: Select Channel 1.
- 1: Select Channel 2.
- D13: Power Down (PD)
- 0: Normal operation.
- 1: Power down mode.
- D12: Reserved
- Always set to 0.
Example Write Sequence
- Select the Device:
- Set CS low.
- Shift in Control and Data Bits:
- Shift in 16 bits of data, starting with the control bits.
- Update the DAC:
- Set LDAC low to transfer the data to the DAC registers.
- Set LDAC high to complete the update.
- Deselect the Device:
- Set CS high.
Power Down Mode
- To put the device into power-down mode, set the PD bit (D13) to 1.
- In power-down mode, the device consumes minimal power, and the outputs are set to a high-impedance state.
Reset
- The device does not have a dedicated reset pin. To reset the device, cycle the power or set all DAC registers to zero by writing to them.
Notes
- Ensure that the supply voltage (VDD) is within the specified range to avoid damage to the device.
- Use appropriate decoupling capacitors near the VDD and VSS pins to minimize noise and ensure stable operation.
- For optimal performance, use a clean and stable clock source for SCLK.
This table and instructions should provide you with the necessary information to use the AD7248JN effectively.
(For reference only)Inquiry - AD7248JN
