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Specifications
SKU: 5249286
IC 128M X 8 EEPROM 3V, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48, Programmable ROM
| Parameter | Description | Value |
|---|---|---|
| Device Type | Non-Volatile Static RAM (NVSRAM) | - |
| Memory Size | Total Memory Capacity | 128 Mbit (16 M x 8) |
| Data Retention | Data Retention Time at 85°C | 10 years |
| Supply Voltage | VCC Operating Range | 1.7V to 1.95V |
| Standby Current | Typical Standby Current (VCC = 1.8V) | 1 μA |
| Active Current | Typical Active Current (VCC = 1.8V, fCLK = 100 MHz) | 40 mA |
| Access Time | Typical Access Time (tAA) | 10 ns |
| Package Type | Package | 48-pin FBGA (Fine Pitch Ball Grid Array) |
| Operating Temperature | Industrial Temperature Range | -40°C to +85°C |
| Write Cycle | Write Cycle Time (tWC) | 35 ns |
| Write Enable | Write Enable Low to High (tWELH) | 5 ns |
| Write Disable | Write Disable High to Low (tWDLH) | 5 ns |
| Hold Time | Address and Control Hold Time (tAH) | 5 ns |
| Clock Frequency | Maximum Clock Frequency | 100 MHz |
| Data Output Hold Time | Data Output Hold Time (tOH) | 5 ns |
| Data Output Setup Time | Data Output Setup Time (tDS) | 5 ns |
| Data Input Setup Time | Data Input Setup Time (tIS) | 5 ns |
| Data Input Hold Time | Data Input Hold Time (tIH) | 5 ns |
| Power Down Mode | Power Down Mode Entry (PD# Low) | - |
| Power Down Exit | Power Down Mode Exit (PD# High) | - |
| Package Dimensions | Package Dimensions (FBGA) | 10 mm x 14 mm x 1.2 mm |
Instructions for Use:
Power Supply:
- Ensure the supply voltage (VCC) is within the specified range of 1.7V to 1.95V.
- Connect the ground (GND) pin to a stable ground reference.
Clock Signal:
- Apply a clock signal (CLK) with a frequency up to 100 MHz.
- The clock signal should be clean and free from excessive noise.
Address and Data Lines:
- Connect the address lines (A0-A23) to the appropriate address bus.
- Connect the data lines (DQ0-DQ7) to the data bus.
Control Signals:
- Use the chip enable (CE#), output enable (OE#), and write enable (WE#) signals to control read and write operations.
- Ensure the hold times and setup times for these signals are met as specified in the table.
Power Down Mode:
- To enter power down mode, set the power down signal (PD#) low.
- To exit power down mode, set the power down signal (PD#) high.
Data Retention:
- Store the device in a temperature-controlled environment to ensure data retention for up to 10 years at 85°C.
Handling:
- Handle the device with care to avoid static damage.
- Follow proper soldering and handling procedures for the FBGA package.
Testing:
- Perform initial testing to verify functionality and ensure all parameters are within the specified limits.
For detailed application notes and further information, refer to the device datasheet provided by the manufacturer.
(For reference only)Inquiry - TC58NVG0S3ETA00
