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Specifications
SKU: 8917273
IC PSRAM 128M PARALLEL 54VFBGA
| Parameter | Description | Value |
|---|---|---|
| Device Type | Type of Memory Device | SDRAM |
| Memory Organization | Data Width x Number of Banks x Number of Rows x Number of Columns | 16M x 32 |
| Density | Total Memory Density | 512 Mb |
| Package | Package Type | FBGA |
| Pin Count | Number of Pins | 84 |
| Supply Voltage (Vdd) | Operating Supply Voltage | 1.8V ± 0.1V |
| Supply Voltage (Vddq) | I/O Supply Voltage | 1.8V ± 0.1V |
| Operating Temperature | Range of Operating Temperatures | -40°C to 85°C |
| Data Rate | Maximum Data Rate | 700 MHz |
| CAS Latency (CL) | CAS Latency | 5, 6, 7 |
| Row Precharge Time (tRP) | Row Precharge Time | 15 ns |
| Row Active Time (tRAS) | Row Active Time | 36 ns |
| Row Cycle Time (tRC) | Row Cycle Time | 48 ns |
| Write Recovery Time (tWR) | Write Recovery Time | 15 ns |
| Exit Self-Refresh to Active Command Time (tXSR) | Exit Self-Refresh to Active Command Time | 75 ns |
| Power Down Exit Time (tXP) | Power Down Exit Time | 12 ns |
| Self-Refresh Entry Time (tSRE) | Self-Refresh Entry Time | 75 ns |
| Minimum Self-Refresh Cycle Time (tCKSRmin) | Minimum Self-Refresh Cycle Time | 64 μs |
| Maximum Self-Refresh Cycle Time (tCKSRmax) | Maximum Self-Refresh Cycle Time | 128 μs |
| Refresh Period (tREFI) | Refresh Period | 7.8 μs |
| Refresh Cycle Time (tRFC) | Refresh Cycle Time | 75 ns |
| Write-to-Read Command Delay (tWRD) | Write-to-Read Command Delay | 2 cycles |
| Read-to-Write Command Delay (tRWR) | Read-to-Write Command Delay | 2 cycles |
| Bank Active to Bank Active Command Time (tRRD) | Bank Active to Bank Active Command Time | 6 ns |
| Address and Control Setup Time (tIS) | Address and Control Setup Time | 0.5 ns |
| Address and Control Hold Time (tIH) | Address and Control Hold Time | 0.2 ns |
| Clock Input High Pulse Width (tCKH) | Clock Input High Pulse Width | 1.5 ns |
| Clock Input Low Pulse Width (tCKL) | Clock Input Low Pulse Width | 1.5 ns |
| Clock Input to Output Access Time (tAA) | Clock Input to Output Access Time | 12 ns |
| Output Enable to Output Access Time (tOE) | Output Enable to Output Access Time | 1.5 ns |
| Output Disable to Output Disable Time (tOH) | Output Disable to Output Disable Time | 1.5 ns |
| Write Data to Clock Skew (tDQSQ) | Write Data to Clock Skew | 0.25 ns |
| Write Data to Write Command Skew (tDQSCK) | Write Data to Write Command Skew | 0.5 ns |
| Write Data to Write Command Skew (tDQSS) | Write Data to Write Command Skew | 0.5 ns |
Instructions for Use:
Power Supply:
- Ensure that the supply voltages Vdd and Vddq are within the specified range of 1.8V ± 0.1V.
- Proper decoupling capacitors should be placed close to the power pins to minimize noise.
Clock Signal:
- The clock signal (CLK) must be stable and within the specified frequency range.
- The clock input high and low pulse widths (tCKH and tCKL) should be at least 1.5 ns each.
Address and Control Signals:
- Address and control signals (A0-A12, BA0-BA1, CS#, RAS#, CAS#, WE#, etc.) should meet the setup and hold time requirements (tIS and tIH).
- Ensure that the address and control signals are stable before the clock edge.
Data Signals:
- For read operations, the data output access time (tAA) is 12 ns from the clock edge.
- For write operations, ensure that the write data to clock skew (tDQSQ) and write data to write command skew (tDQSCK and tDQSS) are within the specified limits.
Refresh Operations:
- The device requires periodic refresh operations to maintain data integrity.
- The refresh period (tREFI) is 7.8 μs, and the refresh cycle time (tRFC) is 75 ns.
Power Management:
- To enter self-refresh mode, use the appropriate command sequence.
- To exit self-refresh mode, wait for the specified exit time (tXSR).
- For power-down mode, use the appropriate command and wait for the power-down exit time (tXP).
Temperature Considerations:
- The device is rated to operate between -40°C and 85°C. Ensure that the operating environment does not exceed these temperature limits.
Handling:
- Handle the device with care to avoid electrostatic discharge (ESD) damage.
- Use proper ESD protection measures during handling and installation.
For detailed information and specific application notes, refer to the datasheet provided by the manufacturer.
(For reference only)Inquiry - MT45W8MW16BGX-701 IT
