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Quad Line Receiver Features: rn High Speed: tpd = 10 ns (typ) at VCC = 5 V rn Low Power Dissipation: ICC = 4 mA (max) rn High Noise Immunity Characteristic of CMOS Devices rn Inputs Compatible with TTL and MOS Levels rn Outputs Source/Sink 24 mA rn Operating Voltage Range: 3 V to 18 V rn Outputs Directly Interface to CMOS, NMOS, and TTL rn Balanced Propagation Delays rn Symmetrical Output Impedance: |IOH| = IOL = 24 mA (min) rn Outputs Can Be Disabled Independently rn Package: DIP-14 Applications: rn Data Communication rn Digital Logic rn Digital Signal Processing rn Computer Peripherals rn Automotive Electronics rn Industrial Control (For reference only)